1. Field of the Invention
The present invention relates to an etching method, and more particularly to a method for etching a metal layer of a display panel.
2. Description of Related Art
Nowadays, displays have served as major communication interfaces between humans and machines. Thus, users may get information from displays and then control the operation of apparatuses. Particularly, the liquid crystal displays (LCDs) have become mainstream display products. In general, an LCD mainly includes a thin film transistor (TFT) array substrate, a color filter substrate, and a liquid crystal layer sandwiched between the two substrates. Here, each of the TFTs including a gate, a channel layer, a source and a drain is mainly used to control the data input into a pixel of the LCD.
FIG. 1 is a schematic cross-sectional view illustrating one of the TFTs in the conventional TFT array substrate. Referring to FIG. 1, a TFT 110 disposed on a substrate 100 includes a gate 111, a gate insulating layer 112, a channel layer 113, a source 114a, a drain 114b, and a passivation layer 115. In addition, a pixel electrode 120 is electrically connected to the drain 114b through a contact 115a in the passivation layer 115. The method for fabricating said gate 111, said gate insulating layer 112, said channel layer 113, said source 114a, said drain 114b, and said passivation layer 115 mainly includes performing several thin film deposition processes, lithographic processes, and etching processes repeatedly, such that the aforementioned devices are formed on the substrate 100.
The structure of the metal layer of the TFT array substrate poses a significant impact on the electrical performance of the TFTs. If the width of the metal line is poorly formed, it affects the electrical characteristics of the TFT. Not only the performance of the TFT is reduced, but the functions of the TFT array substrate are influenced.
For example, if the line width of the metal lines is not uniform, structural differences among the TFTs then occur. The different electrical characteristics of the TFTs lead to undesirable displaying quality of the display. Moreover, if a chamfer is formed at the metal layer after the etching process, the capability of step coverage of a thin film is then deteriorated in a successive thin film deposition process, thus resulting in defects of the TFTs and failure of the devices. Furthermore, the formation of the chamfer brings about a point discharge effect on the devices, therefore making the TFTs fragile and having a negative influence on the performance and the life span of the displays.
Generally speaking, the etching process performed on the metal layer includes a dry etching process and a wet etching process. With the growing demands for larger-sized TFT panels and substrates, an increase of glass substrates in size results in various issues in the current manufacturing process if the dry etching process is performed to pattern the metal layer of the TFT. For example, it is required to provide a larger vacuum environment when a larger glass substrate is placed into a dry etching chamber to perform the dry etching process. Thereby, the cost of exhausting gases out of the large vacuum environment is certainly increased, and it is rather difficult to maintain uniformity of the etching plasma in the large dry etching chamber, thus bringing about non-uniformity of etching.
To overcome said shortcomings, a method of two-step etching is disclosed in U.S. Pat. No. 6,218,821 to solve the problems arisen from the formation of the chamfer at the metal layer. In the related art, a wet etching process is conducted to etch an upper barrier layer and a main metal layer. Then, a dry etching process is performed to etch a lower barrier layer and a channel layer of a TFT device. However, said method including two-step etching not only requires an increase in the number of machines and in costs of manufacturing the TFTs, but also causes undesired metal patterns, thus resulting in loose control of the quality of the TFTs.
Furthermore, the method for fabricating the TFTs disclosed in US Publication No. US 2004/004220 provides a dry etching method comprising multiple steps by using different gases, so as to prevent the formation of the chamfer at the metal layer. Comparatively speaking, this related art requires neither an increase in the number of machines nor sufficient costs incurred in the manufacturing process. However, in terms of an even larger TFT array substrate, the dry etching method still faces the problems of uniformity of etching and the operating costs.
To resolve the issues arisen from etching the metal layer by using the dry etching process, it is common to conduct the wet etching process to etch the metal layer in the manufacturing process of TFTs. A process of patterning one of the metal layers by wet etching in the conventional TFT manufacturing process is described below for further illustration.
FIGS. 2A to 2B are schematic cross-sectional flow charts illustrating a fabrication process of patterning a metal layer through the wet etching method in a conventional process of manufacturing the TFT array substrate. Referring to FIG. 2A, a gate 111, a gate insulating layer 112, a channel layer 113, a metal layer 114, and an mask 130 are successively formed over the substrate 100. Then, a wet etching process is performed to remove the metal layer 114a uncovered by the mask 130. Then, referring to FIG. 2B, the source 114a and drain 114b are formed after the etching process is performed on the metal layer 114. Finally, the mask 130 is removed.
The disadvantages of the increase in costs and non-uniformity of etching in the dry etching process can be prevented when the wet etching process is applied to the process of manufacturing large-sized panels. However, the wet etching process is an isotropic etching process i.e. it has a greater lateral etching rate, the etching process performed on the metal layer causes the problems of an excessive lateral etching amount, further resulting in the formation of the chamfer at the metal layer 114 as shown in FIG. 2B and in an uneven profile of the metal layer 114.
FIG. 2C is a schematic cross-sectional view illustrating a formation of other film layers on the metal layer with the chamfer. Referring to FIG. 2C, when other film e.g. the passivation layer 115 is continuously deposited on the metal layer 114, the capability of step coverage of the passivation layer 115 is reduced due to the existence of the chamfer. Thus, defects or point discharge effects are likely to occur at the tip 116, further leading to failure of the devices.
Additionally, the chamfer at the metal layer or the uneven profile thereof results in non-uniformity of width of the metal lines in the TFT array substrate. The consequential differences in electrical characteristics of each TFT device then affect the optical characteristics of the display panel using the TFT array substrate and cause mura defect. This significantly reduces the displaying quality of the panel.
It can be deduced that one of the critical factors to evaluate the performance of the LCD is the way to decrease the lateral etching amount of the metal layer during the wet etching process. Thereby, the formation of the chamfer can be prevented after the metal layer is etched and a desirable profile of the metal layer can be further obtained.
In order to etch the metal layer through the wet etching process without forming the chamfer due to the fast lateral etching rate, an annealing process is performed after the formation of the metal layer to form a layer of fine crystal grains thereon, as is provided in Taiwan Patent No. I584914. Since the layer of the fine crystal grains has a faster etching rate than the metal layer does, the formation of the chamfer at the metal layer can be avoided.
On the other hand, a sacrificial layer, with a faster etching rate than the metal layer, is provided in U.S. Pat. No. 6,297,161. The sacrificial layer disposed on the metal layer also prevents the formation of the chamfer. All of the related arts discussed above, however, result in an increase in the manufacturing costs, and the etchant inactivates as used repeatedly. Thus, the lateral etching amount is not under an effective control even though the etchant is replaced by a new one.
According to the aforesaid methods for reducing the formation of the chamfer, the manufacturing costs of the TFT array substrate increase regardless of performing the annealing process to change the characteristics of the upper film on the metal layer, or of forming the sacrificial layer. Moreover, with the change of the characteristics of the upper film or the formation of the sacrificial layer, the characteristics of the TFT devices change. This can be one of the factors affecting the characteristics of the TFT devices, and it is even more unlikely to control the electrical characteristics of the TFT devices and to monitor the yield rate. Thus, a better solution is still required.
One of the most common manufacturing processes utilized in the industry is to increase the thickness of the passivation layer or the insulating layer in accordance with Taiwan Patent No. I586223. Alternatively, a planarization layer is added to reduce the influence on the electrical characteristics of the TFTs due to the formation of the chamfer. Still, the increase in materials and costs during said manufacturing processes does exist and brings about greater height differences of the TFTs. Hence, the subsequent alignment process is affected, and the displaying quality of the displays is further reduced.
In general, when the nitric acid solution reacts with the metal layer e.g. Al layer, two of chemical reactions occur,Al+HNO3→Al2O3+H2O+NO2  (reaction 1)Al+HNO2→Al2O3+H2O+NO2  (reaction 2)
Here, the nitride dioxide (NO2) produced in reaction 1 reacts with water and produces nitrous acid (HNO2). HNO2 oxidizes the Al metal and produces aluminum oxide (Al2O3), and the valence of the nitrogen atoms in HNO2 is +3, which is relatively unstable to a +5 valence of the nitrogen atoms in the nitric acid. Therefore, reaction 2 has a reaction rate higher than that of reaction 1, such that reaction 1 is the rate determining step (RDS) when the Al metal reacts with the nitric acid solution.
It should be understood that the etchant used in the conventional etching process is, as a rule, the nitric acid solution, and the concentration thereof usually is in a range from 0.2% to 6.0%. The concentration is raised to 1.5%˜10% when the etchant is replaced, and reaction 2 is then induced. Thereby, the lateral etching rate of the Al metal is increased to a range between 100 Å/sec and 180 Å/sec, and the ratio of the maximum lateral etching amount to the minimum etching amount is about 0.85˜1.0. Thus, the occurrence of reaction 2 and the corresponding reaction with the Al metal are the key factors of the formation of the chamfer at the Al metal layer and non-uniformity of lateral etching.
Another well-known manufacturing process to reduce the formation of the chamfer at the metal layer is performed by adjusting a recipe of the etching solution e.g. by changing the ratio of composition of the nitric acid or by adding a surfactant to decrease the etching reaction rate. Thereby, the lateral etching amount can be controlled to reduce the formation of the chamfer. However, given that the chemical concentration of the etchant is decreased, the etching process using said etchant cannot be frequently and constantly performed. In other words, the performance of the etchant is significantly reduced after the etching process is performed on few substrates, such that the replacement frequency of the etchant is high and the manufacturing cost is increased.